Job Description

Job Description

OVERVIEW

This opportunity is with a well-established semiconductor company that has been at the forefront of RF integrated circuit development for mobile and wireless applications. The company is known for tackling complex design challenges and delivering advanced solutions that enable high-performance products used across the globe.

Engineers here are part of an environment that values innovation, precision, and technical depth. The work directly influences large-scale consumer technologies, offering visibility and impact beyond the lab. The company fosters close collaboration among experienced specialists in RF, packaging, and system design, creating a setting where technical expertise is sharpened and career growth is supported.

For professionals who thrive on solving demanding engineering problems and want their contributions to be reflected in widely deployed products, this role offers a chance to work at the cutting edge of RFIC design.

RESPONSIBILITIES

• Design, simulate, and validate CMOS RFIC circuits, including blocks such as LNAs, mixers, power amplifiers, and PLLs.
• Define and provide direction for RFIC floorplanning and layout activities.
• Offer recommendations on IC packaging and PCB layout to enhance RF performance.
• Participate in silicon bring-up through measurements, characterization, and debugging.
• Collaborate with cross-functional teams to ensure successful design execution.
• Travel internationally to support design and production activities as required.

REQUIREMENTS

• Graduate degree (MS or higher) in Electrical Engineering or a related discipline.
• Minimum of 5 years’ experience designing CMOS RFICs for mobile communication standards such as GSM, CDMA, GPRS, UMTS, or LTE, with a proven track record of taking designs into high-volume manufacturing.
• Strong background in advanced CMOS process technologies and the design trade-offs associated with deep submicron nodes.
• Hands-on experience with Cadence custom IC design environments and circuit-level simulation tools.
• Familiarity with RF system concepts, such as link budget analysis, is desirable.
• Knowledge of transmission line behavior and electromagnetic theory is considered a plus.
• Experience developing custom passive devices on-chip (e.g., inductors or transformers) is advantageous.
• Exposure to noise coupling challenges in IC design and strategies for mitigation is beneficial.
• Practical understanding of PCB layout techniques and/or IC packaging design is an added advantage.

INTERESTED

We are moving quickly to present qualified candidates for this role. For more information, please contact Jaimie Javier at PER International on LinkedIn or send your CV to jaimie@per-international.com

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